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data sheet 1-to-12, differential hcsl fanout buffer 8v31012 8v31012 revision 1 10/21/15 1 ?2015 integrated device technology, inc. 48-pin, 7mm x 7mm vfqfn package v dd q2 gnd nq1 q1 v dd nq0 q0 nq3 q3 nq2 v dd q7 v dd q8 nq8 gnd q9 nq9 v dd nq6 v dd nq7 q6 gnd iref q4 nq4 v dd q5 nq5 v dd v dd nc v dd gnd v dd nc nq11 q11 v dd nq10 q10 nc v dd nclk clk gnd 36 35 34 33 32 31 30 28 29 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 9 8 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 8v31012 general description the 8v31012 is a 1-to-12 differential hcsl fanout buffer. the 8v31012 is designed to translate any differential signal levels to differential hcsl output levels. an external reference resistor is used to set the value of the current supplied to an external load/termination resistor. the load resistor value is chosen to equal the value of the characteristic line impedance of 50 ? . the 8v31012 is characterized at an operat ing supply voltage of 3.3v. the differential hcsl outputs, accurate crossover voltage and duty cycle make the 8v31012 ideal for interfacing to pci express and fbdimm applications. features ? twelve differential hcsl outputs ? translates any differential input signal (lvpecl, lvhstl, lvds, hcsl) to hcsl levels without external bias networks ? maximum output frequency: 250mhz ? output skew: 265ps (typical) ? v oh : 850mv (maximum) ? full 3.3v supply voltage ? available in lead-free (rohs 6) package ? -40c to 85c ambient operating temperature clk nclk iref q11 nq11 q10 nq10 q9 nq9 q8 nq8 q7 nq7 q6 nq6 q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 q5 nq5 pin assignment block diagram
1-to-12, differential hcsl fanout buffer 2 revision 1 10/21/15 8v31012 data sheet pin description and pin characteristic tables table 1. pin descriptions number name type description 1 q0 output differential output pair. differ ential hcsl interface levels. 2 nq0 output differential output pair. differ ential hcsl interface levels. 3v dd power power supply pin. 4 q1 output differential output pair. differ ential hcsl interface levels. 5 nq1 output differential output pair. differ ential hcsl interface levels. 6gndpower power supply ground. 7 q2 output differential output pair. differ ential hcsl interface levels. 8 nq2 output differential output pair. differ ential hcsl interface levels. 9v dd power power supply pin. 10 q3 output differential output pair. differ ential hcsl interface levels. 11 nq3 output differential output pair. differ ential hcsl interface levels. 12 v dd power power supply pin. 13 gnd power power supply ground. 14 iref input external fixed precision resistor (950 ? ) from this pin to ground provides a reference current used for differential current -mode qx, nqx clock outputs. 15 q4 output differential output pair. differ ential hcsl interface levels. 16 nq4 output differential output pair. differ ential hcsl interface levels. 17 v dd power power supply pin. 18 q5 output differential output pair. differ ential hcsl interface levels. 19 nq5 output differential output pair. differ ential hcsl interface levels. 20 v dd power power supply pin. 21 v dd power power supply pin. 22 nc unused no connect. 23 v dd power power supply pin. 24 gnd power power supply ground. 25 q6 output differential output pair. differ ential hcsl interface levels. 26 nq6 output differential output pair. differ ential hcsl interface levels. 27 v dd power power supply pin. 28 q7 output differential output pair. differ ential hcsl interface levels. 29 nq7 output differential output pair. differ ential hcsl interface levels. 30 v dd power power supply pin.
revision 1 10/21/15 3 1-to-12, differential hcsl fanout buffer 8v31012 data sheet output driver current the 8v31012 outputs are hcsl differential current dr ive with the current being set with a resistor from i ref to ground. for a single load and a 50 : pc board trace, the drive current would typically be set with a r ref of 950 : which products an i ref of 1.16ma. the i ref is multiplied by a current mirror to an output drive of 12*1.16ma or 13.90ma. see figure 1 for current mirror and output drive details. r ref 950
1-to-12, differential hcsl fanout buffer 4 revision 1 10/21/15 8v31012 data sheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functio nal operation of product at t hese conditions or any conditions beyond those listed in the dc cha racteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o -0.5v to v dd + 0.5v storage temperature, t stg -65 q c to 150 qc dc electrical characteristics item rating maximum junction temperature 125c table 2a. power supply dc characteristics, v dd = 3.3v5%, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v i dd power supply current output unterminated 105 ma table 2b. differential dc characteristics, v dd = 3.3v5%, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units i ih input high current clk, nclk v dd = v in = 3.465v 5 a i il input low current clk, nclk v dd = 3.465v, v in = 0v 5 a v pp peak-to-peak voltage 1 note 1. v il should not be less than -0.3v. 0.15 1.3 v v cmr common mode input voltage 1, 2 note 2. common mode input voltage is defined as v ih. gnd + 0.5 v dd ? 0.85 v
revision 1 10/21/15 5 1-to-12, differential hcsl fanout buffer 8v31012 data sheet ac electrical characteristics table 3. hcsl ac characteristics, v dd = 3.3v5%, t a = -40c to 85c 1, 2, 3 symbol parameter test conditi ons minimum typical maximum units f max output frequency 250 mhz t pd propagation delay 4 measured on at v ox 2.35 2.75 ns t sk(o) output skew 5, 6 measured on at v ox 265 395 ps t sk(pp) part-to-part skew 6, 7 335 ps t jit buffer additive phas e jitter, rms; refer to additive phase jitter section clk = 200mhz, integration range: 12khz ? 30mhz 0.15 ps v max absolute max output voltage 8 ? ? 150mhz 500 850 mv v min absolute min output voltage 8 ? ? 150mhz -150 150 mv v cross absolute crossing voltage 9, 10, 11 250 550 mv ? v cross total variation of v cross over all edges 9, 10, 12 140 mv rise/fall edge rate 13, 14 0.6 4.0 v/ns rise/fall time matching 15 20 % odc output duty cycle 16 45 55 % note 1. electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow gr eater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. note 2. current adjust set for v oh = 0.7v. measurements refer to pciex outputs only. note 3. characterized using an r ref value of 950 ? resistor. note 4. measured from the differential input cro ss point to the differential output crossing point. note 5. defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the differential output cross point. note 6. this parameter is defined in accordance with jedec standard 65. note 7. defined as skew between outputs on different devices opera ting at the same supply voltage, same frequency, same tempera ture and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross po int. note 8. measurement using r ref = 950 ? , r load = 50 ? . note 9. measurement taken from single-ended waveform. note 10. measured at crossing point where the instantaneous voltage value of the risi ng edge of qx equals the falling edge of n qx. ? see parameter measurement information section. note 11. refers to the total variation fr om the lowest crossing point to the highes t, regardless of which edge is crossing. ref ers to all crossing points for this measurement. see para meter measurement information section. note 12. defined as the total variation of all crossing voltage of rising qx and falling nqx. this is the maximum allowed varia nce in the v cross for any particular system. see parame ter measurement information section. note 13. measurement taken from differential waveform. note 14. measurement from -150mv to +150mv on the differential waveform (derived from qx minus nqx). the signal must be monoton ic through the measurement region for rise and fall time. the 300mv measurement window is centered on the differential zero crossi ng. note 15. matching applies to rising edge rate for qx and falling edge rate for nqx. it is measured using a 75mv window centere d on the median cross point where qx rising meets nqx falling. note 16. assuming 50% input duty cycle. data taken at ? ? 200mhz, unless otherwise specified.
revision 1 10/21/15 6 1-to-12, differential hcsl fanout buffer 8v31012 data sheet additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundament al frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specifications , phase noise measurements have issues relating to the limitations of the measurement equipment. the noise floor of the equipment can be higher or lower than the noise floor of the device. additive phase noise is dependent on both the noise floor of the input source and measurement equipment. the additive phase jitter for this device was measured using a stanford research systems cg635 input source and an agilent e5052 phase noise analyzer. ssb phase noise dbc/hz offset from carrier frequency (hz)
revision 1 10/21/15 7 1-to-12, differential hcsl fanout buffer 8v31012 data sheet applications information recommendations for un used output pins o utputs: differential outputs all unused differential outputs ca n be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. wiring the differential input to accept single-ended levels figure 2 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock is driven from a single-ended 2.5v lvcmos driver and the dc offset (or swing center) of this signal is 1.25v, the r1 and r2 values should be adjusted to set the v1 at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmis sion line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 : applications, r3 and r4 can be 100 : . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection benefits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced while maintaining an edge rate faster than 1v/ns. the datasheet specifies a lo wer differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 2. recommended schematic for wiring a diff erential input to accept single-ended levels
1-to-12, differential hcsl fanout buffer 8 revision 1 10/21/15 8v31012 data sheet differential clock input interface the clk/nclk accepts hcsl, lvds, lvpecl and lvhstl and other differential signals. both differential signals must meet the v pp and v cmr input requirements. figure 3a to figure 3e show interface examples for the clk, nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of t he driver component to confirm the driver termination requirements. for example in figure 3a , the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 3a. clk/nclk input driven by an idt ? open emitter lvhstl driver figure 3b. clk/nclk input driven by a ? 3.3v lvpecl driver figure 3c. clk/nclk input driven by a ? 3.3v hcsl driver figure 3d. clk/nclk input driven by a ? 3.3v lvpecl driver figure 3e. clk/nclk input driven by a 3.3v lvds driver ? r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 zo = 50 clk nclk 3.3v 3.3v lvpecl differential input h csl *r 3 * r4 c l k n c l k 3 . 3v 3 . 3v diff e r e nti a l in p u t 3.3v r1 100 lvds clk nclk 3.3v differential input zo = 50 zo = 50
revision 1 10/21/15 9 1-to-12, differential hcsl fanout buffer 8v31012 data sheet recommended termination figure 4a is the recommended source termination for applications where the driver and receiver will be on a separate pcbs. this termination is the standard for pci express? and hcsl output types. all traces should be 50 ? impedance single-ended or 100 ? differential. figure 4a. recommended source termination (where th e driver and receiver will be on separate pcbs) figure 4b is the recommended termination for applications where a point-to-point connection can be us ed. a point-to-point connection contains both the driver and the receiver on the same pcb. with a matched termination at the receiver, transmission-line reflections will be minimized. in addition, a series resistor (rs) at the driver offers flexibility and can help dampen unwanted reflections. the optional resistor can range from 0 ? to 33 ? . all traces should be 50 ? impedance single-ended or 100 ? differential. figure 4b. recommended termination (where a point-to-point connection can be used) 0-0.2" pci express l1 l1 1-14" driver rs 0.5" max l3 l4 l2 l2 49.9 +/- 5% 22 to 33 +/-5% rt l3 l4 l5 0.5 - 3.5" l5 connector pci express add-in card pci express 0-0.2" pci express 0-0.2" 0-18" l1 l1 rs driver 0.5" max l3 l3 l2 l2 49.9 +/- 5% 0 to 33 0 to 33 rt
1-to-12, differential hcsl fanout buffer 10 revision 1 10/21/15 8v31012 data sheet epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 5 . the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/electrically enhance leadframe base package, amkor technology. figure 5. assembly for exposed pad thermal rel ease path - side view (drawing not to scale) ground plane land pattern solder thermal via exposed heat slug (ground pad) pin pin pad solder pin pin pad solder
revision 1 10/21/15 11 1-to-12, differential hcsl fanout buffer 8v31012 data sheet power considerations this section provides information on power dissi pation and junction temperature for the 8v31012. ? equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8v31012 is the sum of the core power plus the power dissipated in the load(s). ? the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v dd_max * (i dd_max ) = 3.465v *(105ma) = 363.825mw ? power (outputs) max = 44.5mw/loaded output pair ? if all outputs are loaded, the total power is 12 * 44.5mw = 534mw ? total power_ max = (3.465v, with all outputs switching) = 363.825mw + 534mw = 897.825mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 29c/w per table 4 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.898w *29c/w = 111c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 4. thermal resistance ? ja for 48lead vfqfn, e-pad, forced convection ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 29.0c/w 25.4c/w 22.7c/w
1-to-12, differential hcsl fanout buffer 12 revision 1 10/21/15 8v31012 data sheet 3. calculations and equations. the purpose of this section is to calculate power dissipation on the ic per hcsl output pair. hcsl output driver circuit and termination are shown in fi gure 6. v ddo v out r l 50 ?
revision 1 10/21/15 13 1-to-12, differential hcsl fanout buffer 8v31012 data sheet reliability information transistor count the transistor count for 8v31012 is: 843 table 5. ? ja vs. air flow table for a 48 lead vfqfn, e-pad, forced convention ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 29.0c/w 25.4c/w 22.7c/w
table 6. package dimensions for 48-lead package 1 1-to-12, differential hcsl fanout buffer 14 revision 1 10/21/15 8v31012 data sheet 48-lead vfqfn (nl) package ou tline and package dimensions note 1. the drawing and dimension data originates from idt package outline drawing psc-4203, rev 04. all dimensions are in millimeters. all angles are in degrees. symbol dimensions min nom max d 7.00 bsc e 7.00 bsc d2 5.50 5.65 5.80 e2 5.50 5.65 5.80 l 0.35 0.40 0.45 e 0.50 bsc n48 a 0.80 0.85 0.90 a1 0.00 0.02 0.05 a3 0.2 ref b 0.18 0.25 0.30 ?
revision 1 10/21/15 15 1-to-12, differential hcsl fanout buffer 8v31012 data sheet package outline and packag e dimensions (continued) recommended land pattern note: the recommended land pattern originates from idt package outline drawing psc r 4203, rev04 . 1. all dimensions are in millimeters. angles are in degrees. 2. top down view. as viewed on pcb. 3. component outline show for reference in black. 4. land pattern in blue. nsmd pattern assumed. 5. land pattern recommendation per ipc r 7351b generic requirement for surface mount design and land pattern.
1-to-12, differential hcsl fanout buffer 16 revision 1 10/21/15 8v31012 data sheet ordering information table 7. ordering information part/order number marking package shipping packaging temperature 8V31012NLGI idt8V31012NLGI 48 lead vfqfn, lead-free tray -40c to 85c 8V31012NLGI8 idt8V31012NLGI 48 lead vfqfn, lead-free tape & reel -40c to 85c
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